vllm.attention.ops.nki_flash_attn
_flash_attention_core
¶
_flash_attention_core(
q_local_tile,
k,
v,
o_buffer,
l_buffer,
m_buffer,
kernel_dtype,
acc_type,
tile_mask,
use_causal_mask,
q_tile_idx=None,
initialize=False,
LARGE_TILE_SZ=2048,
B_P_SIZE=128,
B_F_SIZE=512,
B_D_SIZE=128,
qk_res_buffer=None,
)
The flash attention core function to calculate self attention between a tile of q and a block of K and V. The q_local_tile has (B_P_SIZE, B_D_SIZE) The K and V have shape (B_D_SIZE, LARGE_TILE_SZ), whose free dimension will be split into size B_F_SIZE tiles
The results are stored in the following three buffers o_buffer: (B_P_SIZE, d) l_buffer: (B_P_SIZE, 1) m_buffer: (B_P_SIZE, 1)
All IO buffers are in SBUF.
Source code in vllm/attention/ops/nki_flash_attn.py
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flash_attn_varlen_nkifunc
¶
flash_attn_varlen_nkifunc(
query,
key,
value,
kv_cache,
block_table,
attn_mask,
n_kv_head=None,
head_size=None,
LARGE_TILE_SZ=2048,
mixed_precision=True,
)
Compute flash paged attention for variable length sequences.
This function is a wrapper around the flash attention NKI kernel. It takes in the following arguments: - query: (1, n_heads, d, seq_q) - key: (1, n_kv_heads, d, seq_k) - value: (1, n_kv_heads, seq_v, d) - kv_cache: (2, n_blocks, n_kv_heads, block_size, d) - block_tables: (n_active_blocks, ) - attn_mask: (seq_q, n_active_blocks * block_size + seq_q)
Notes
- attn_mask must be reordered outside using
reorder_context_mask
- Key/value cache layout must be (n_blocks, n_kv_heads, block_size, d) for better DMA throughput
Source code in vllm/attention/ops/nki_flash_attn.py
flash_paged_attention
¶
flash_paged_attention(
query,
key,
value,
kv_cache,
block_tables,
mask,
softmax_scale=None,
mixed_precision=True,
LARGE_TILE_SZ=2048,
return_debug_tensors=False,
)
Flash PagedAttention Forward Kernel.
IO tensor layouts
- query: shape (1, n_heads, d, seq_q)
- key: shape (1, n_kv_heads, d, seq_k)
- value: shape (1, n_kv_heads, seq_v, d)
- kv_cache: (2, num_blocks, n_kv_heads, block_size, d)
- block_tables: (num_active_blocks, )
- mask: (seq_q, num_active_blocks * block_size + seq_q)
-
o: shape (1, n_heads, seq_q, d)
-
This kernel requires seq_k == seq_v
- We use continuous batching by default, so the batch dimension is always 1, and different requests are concatenated along sequence dimension.
- We use paged cache blocks (kv_cache) to store KV cache.
IO tensor dtypes
- This kernel assumes all IO tensors have the same dtype except for block_tables (int32) and mask (int32)
- If mixed_precision is True, then all Tensor Engine operation will be performed in bfloat16 and accumulation will be performed in float32. Otherwise the intermediates will be in the same type as the inputs.
Compile-time Constants
- softmax_scale: scaling for softmax, is None, default is
1.0/(d**0.5)
- mixed_precision: flag to set non-matmul ops in fp32 precision, default
is set to
true
, if false, we use same precision as input types - LARGE_TILE_SZ:
default=2048
, size of the kv tile size for attention computation reduction
GQA support Notes
the spmd kernel for launching kernel should be on kv_heads instead of nheads
Example usage
MHA: q: [b, h, d, s], k: [b, h, d, s], v: [b, h, s, d]
usage: flash_fwd[b, h](q, k, v, ...)
GQA: q: [b, h, d, s], k: [b, kv_h, d, s], v: [b, kv_h, s, d]
usage: flash_fwd[b, kv_h](q, k, v, ...)
Source code in vllm/attention/ops/nki_flash_attn.py
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is_power_of_2
¶
load_block_tables
¶
Load block tables from HBM into SRAM
block_tables_hbm
has shape (num_tiles * num_blocks_per_tile, )
.
In case num_tiles > B_P_SIZE
, we need further tile num_tile
dimension.
Source code in vllm/attention/ops/nki_flash_attn.py
load_kv_tile_from_cache
¶
load_kv_tile_from_cache(
cur_k_tile,
cur_v_tile,
kv_cache,
block_tables,
large_k_tile_idx,
num_blocks_per_large_tile,
tiled_block_size,
B_P_SIZE,
B_D_SIZE,
)
Load KV cache and transform Key and Value into layout required by Matmul
Vectorized DMA Load layout: Key and Value: (par_dim(B_P_SIZE), seqlen_kv // B_P_SIZE * B_D_SIZE)
Layout used by attention matmuls: Key: (par_dim(B_D_SIZE), seqlen_kv) Value: (seqlen_kv // B_P_SIZE, par_dim(B_P_SIZE), B_D_SIZE) equivalent to (par_dim(B_P_SIZE), seqlen_kv // B_P_SIZE * B_D_SIZE)
Source code in vllm/attention/ops/nki_flash_attn.py
load_v_tile
¶
Source code in vllm/attention/ops/nki_flash_attn.py
reorder_context_mask
¶
Reorder the mask to make it compatible with the flash attention kernel.
We vectorize KV cache read to improve DMA utilization. However, the layout that maximizes DMA bandwidth changes the order tokens are consumed.
The token layout (inner 2 dimensions) after vectorized load is (B_P_SIZE,
tiled_block_size) in a tile of B_P_SIZE * tiled_block_size
tokens. And
each step the engine consumes a column (rather than a row) of B_P_SIZE
tokens. Therefore, the tokens are visited in a strided way.
To make sure mask matches the order tokens are consumed, we need to properly transpose mask.
Source code in vllm/attention/ops/nki_flash_attn.py
reshape_and_cache
¶
Writes key-value pairs to the KV cache at specified positions.
Parameters:
Name | Type | Description | Default |
---|---|---|---|
key
|
Tensor
|
Key tensor with shape (num_tokens, n_kv_head, d_head) |
required |
value
|
Tensor
|
Value tensor with shape (num_tokens, n_kv_head, d_head) |
required |
kv_cache
|
Tensor
|
Key/value cache tensor with shape (2, num_blocks, n_kv_head, block_size, d_head) |
required |
slot_mapping
|
Tensor
|
Mapping tensor indicating cache positions with shape (num_tokens) |
required |
Returns:
Name | Type | Description |
---|---|---|
None |
None
|
Updates the kv_cache tensor in-place |
Source code in vllm/attention/ops/nki_flash_attn.py
transform_block_tables_for_indirect_load
¶
transform_block_tables_for_indirect_load(
block_tables,
block_size_tiling_factor,
num_head,
head_id,
)
This function does two things:
1. calculate new block_tables
for a head_id
after flattening
num_block
, num_head
, and block_size_tiling_factor
dimensions
2. transpose the result so that block_table
for each tile is mapped to
SBUF Partition dimension for vectorized DMA
Tiling trick to further improve DMA performance:
Given KV cache shape (num_block, num_head, block_size, D)
, when loading M
blocks of a given head_id
from HBM, the load cache[block_tables,
head_id]
has shape (M, block_size, D)
. If M < B_P_SIZE = 128, DMA may not
fully utilize hardware parallelization. The solution is to tile block_size
into (block_size_tiling_factor, tiled_block_size)
s.t. M *
block_size_tiling_factor = B_P_SIZE
. After tiling, KV cache has shape
(num_block, num_head, block_size_tiling_factor, tiled_block_size, D)
.
Note: We don't further tile D dimension as small DMA size also hurts performance.
Source code in vllm/attention/ops/nki_flash_attn.py
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